Digital circuits such as microprocessors, memory circuits, busses and other devices are frequently synchronous circuits in which operations may be synchronized by one or more clock signals. A clock signal is typically a periodic signal having a particular frequency. However, due to circuit aging effects, the clock signals may change over time. Thus, for example, the duty cycle of a clock signal at a particular frequency may change due to circuit aging effects. Also, the timing relationship between two or more clock signals may become skewed due to circuit aging. Such changes can alter or disrupt the operation of synchronous circuits.
Copending U.S. application Ser. No. 10/745,427, filed Dec. 23, 2003 (publication No. U.S. 2005/0134394) entitled “On-Chip Transistor Degradation Monitoring”, by the present applicant and assigned to common assignee, Intel Corporation, is directed to, in one embodiment, an integrated on-chip characterization circuit which includes a selectively enabled ring oscillator to generate a reference oscillating signal, a free-running ring oscillator to generate a free-running oscillating signal, and a comparison circuit coupled to the selectively enabled ring oscillator and the free-running ring oscillator. From the reference oscillating signal and the free-running oscillating signal, the comparison circuit determines a measure of transistor degradation. The selectively enabled ring oscillator when disabled, avoids or retards degradation of the of the selectively enabled ring oscillator. More specifically, sources and drains of transistors of the selectively enabled ring oscillator are coupled to the same potential to avoid or retard degradation of the transistors of the selectively enabled ring oscillator.